This option is extremely useful for post route optimizations for 7 Series designs. I recently had a design where route_design ended with 980 ps of negative setup slack and phys_opt_design -directive AggressiveExplore was able to reduce it to 69 ps of negative slack. At that point I moved one cell which was at the worst case path and another sequence of route_design -tns_cleanup + phys_opt_design -directive AggressiveExplore managed to push it to 15 ps of negative slack. At which point I stopped optimizing.
It seems Xilinx has already released some tools for Kintex-8 and Virtex-8. Maybe even chips are in the wild. I wonder if they are 20nm parts. It would be so nice to get an eval board if they do exist. One reference to Virtex-8 is here: http://www.xilinx.com/innovation/research-labs/keynotes/RAW2012_keynote.pdf
Here is a report from Digitimes which says 8 series parts will be manufactured on TSMC 20nm process: http://www.digitimes.com/news/a20121115PB200.html
I’ve been working on a design which is implemented on a Xilinx Series 7 FPGA. I had a -50ps timing violation and it seemed that the placement of the cells in the critical path could have been done better. In an ASIC flow this would be quite easy to fix but previous generation of Xilinx tools didn’t support this functionality easily. The current Vivado toolset is significantly better. It turns out after a design placed & routed, it is possible to move cells with “unplace_cells, place_cells” commands and run route_design again which in turn repairs all the generated DRCs and generates another valid implementation. Kudos to Xilinx for delivering a good set of tools worthy of the Series 7 FPGAs.
BTW the final timing result is -8ps which is good enough for this prototype; although fixing it would not have been difficult if needed.
I have been using Vivado toolset for a month now, on & off as I have current designs on Spartan 6 and Virtex 5 which need RTL improvement so ISE is still in use but I find myself wanting to go back to the Kintex project so that I can use the Vivado back-end tools more and more. I am also working on a Zynq system which will replace the existing hardware so future looks nice.
In terms of Vivado back-end, the timing system is a big relief from UCF. Full SDC constraints are supported with an embedded TCL interpreter. So far I have seen one bug where the timing optimizer sometimes hangs while fixing holds but it is rare and I have heard from Xilinx that they know about it and have a plan to fix.
Vivado simulator luckily is not specific to series 7 chips and its UI is slightly better than ISE simulator. One welcome addition is the ability to view buses as analog waveforms which is nice.
Last but not least Vivado HLS is quite interesting too. So far I have written a small amount of fixed-point C++ code and translated it to RTL but not compared to QOR to my existing hand-written RTL but it’s nice to know that there is an option.
Overall Vivado family is evolving nicely and I am pretty happy with the current performance.