Initial impressions of Vivado family toolset from Xilinx



I have been using Vivado toolset for a month now, on & off as I have current designs on Spartan 6 and Virtex 5 which need RTL improvement so ISE is still in use but I find myself wanting to go back to the Kintex project so that I can use the Vivado back-end tools more and more. I am also working on a Zynq system which will replace the existing hardware so future looks nice.
In terms of Vivado back-end, the timing system is a big relief from UCF. Full SDC constraints are supported with an embedded TCL interpreter. So far I have seen one bug where the timing optimizer sometimes hangs while fixing holds but it is rare and I have heard from Xilinx that they know about it and have a plan to fix.
Vivado simulator luckily is not specific to series 7 chips and its UI is slightly better than ISE simulator. One welcome addition is the ability to view buses as analog waveforms which is nice.
Last but not least Vivado HLS is quite interesting too. So far I have written a small amount of fixed-point C++ code and translated it to RTL but not compared to QOR to my existing hand-written RTL but it’s nice to know that there is an option.
Overall Vivado family is evolving nicely and I am pretty happy with the current performance.

2 thoughts on “Initial impressions of Vivado family toolset from Xilinx

  1. Pingback: data recovery

  2. Pingback: Trenton Gao

Leave a Reply