I’ve been working on a design which is implemented on a Xilinx Series 7 FPGA. I had a -50ps timing violation and it seemed that the placement of the cells in the critical path could have been done better. In an ASIC flow this would be quite easy to fix but previous generation of Xilinx tools didn’t support this functionality easily. The current Vivado toolset is significantly better. It turns out after a design placed & routed, it is possible to move cells with “unplace_cells, place_cells” commands and run route_design again which in turn repairs all the generated DRCs and generates another valid implementation. Kudos to Xilinx for delivering a good set of tools worthy of the Series 7 FPGAs.
BTW the final timing result is -8ps which is good enough for this prototype; although fixing it would not have been difficult if needed.