AR #65413 is a really annoying answer record from Xilinx. They are basically saying that a perfectly legitimate piece of code won’t work in Vivado synthesis and they have no intention of fixing it. Alas the following code will not work:

generate
  for (g=0; g < D; g++) begin: regs
    //string rlocval;
    //localparam string rlocpre = "X0Y";
    //localparam string rloc = {rlocpre, rlocval.itoa(g/8)};
    localparam rlocpre = "X0Y";
    localparam byte rlocbyte = g/8 + 48;
    localparam rloc = {rlocpre, rlocbyte};
    localparam bel[8] = {"AFF", "A5FF", "BFF", "B5FF", "CFF", "C5FF", "DFF", "D5FF"};
    (* RLOC = rloc, BEL = bel[g%8] *) FDRE u(.C(clk), .D(d[g]), .Q(q[g]), .CE(1'b1), .R(1'b0));
  end
endgenerate