In recent generations of Xilinx FPGAs a new feature has been introduced: HARD_SYNC dedicated synchronization registers.
These are hardwired/dedicated blocks with 3 registers specifically designed with synchronization purposes.
It’s possible to configure a hard_sync synchronizer for 2 or 3 stages of shift registers. These should give the best defence against meta-stability while sampling asynchronous signals.

Here is how they are used in Verilog:

HARD_SYNC #(
.INIT(1’b0), // Initial value
.IS_CLK_INVERTED(1’b0), // configurable inverted clock
.LATENCY(2) // 2-3 stage shift register
)
uhardsync (
.DIN(DIN), // input Data
.DOUT(DOUT), // output Data
.CLK(CLK) // Clock
);