In Vivado 2015.3 PTP_ETHERNET are removed by design. To get them back the following tcl command needs to be run:
set_property CONFIG.PCW_EN_PTP_ENET0 1 [get_bd_cells processing_system7_0]
In Vivado 2015.3 PTP_ETHERNET are removed by design. To get them back the following tcl command needs to be run:
set_property CONFIG.PCW_EN_PTP_ENET0 1 [get_bd_cells processing_system7_0]
SystemVerilog has two conversion functions related to the new shortreal type: $bitstoshortreal & $shortrealtobits.
Some simulators support shortreal but don’t implement these functions. I made some simple implementations as regular functions. You can find them here: https://github.com/muzafferkal/shortreal
Again this comes with no support. If you find them useful please send a short email. If you find/fix any issues, please send a longer email 🙂
-K
This is something I have been thinking about for a while. Xilinx has a nice BFM for Zynq but it requires a license to run the AXI3 models. The following open-source AXI (3 for now) BFM is a start to run the Zynq BFM without any license. I have coded and tested enough of this models to verify that the default Zynq test program simulates and passes.
Here is the github project: https://github.com/muzafferkal/axi-bfm
Here is how I tested the models:
* Use Vivado 2015.2
* Create a new microprocessor project with Zynq and name it zynq_example.
* After your project is created, goto zynq_example\zynq_example.srcs\sim_1\imports\base_zynq_design directory and edit zynq_tb.v file which was automatically created.
* Add the following two lines somewhere in the module (this is necessary for Vivado to load the two sv files; otherwise they are not compiled and simulation doesn’t link)
axi3_master_bfm mstr();
axi3_slave_bfm slv();
* Add the two sv files to your project.
* Finally goto zynq_example\zynq_example.srcs\sources_1\ipshared\xilinx.com\processing_system7_bfm_v2_0\xxxxxxxx\hdl
and edit the following three files to rename the instantiation of the axi3_master_bfm and axi3_slave_bfm instances:
processing_system7_bfm_v2_0_axi_master.v
processing_system7_bfm_v2_0_afi_slave.v
processing_system7_bfm_v2_0_axi_slave.v
* At this point, you should be able to simulate the default design, observe that the led’s toggle and the simulation “passes”; Good luck and keep in touch.