SystemVerilog interfaces don’t support hierarchy

I have been trying to design some AXI blocks with SystemVerilog and it seemed like to a good idea to use interface for this purpose

AXI has 5 channels: read and write address, write data, read data and response channels. Of these read and write address channels are identical and other channels have minor differences from each other. As someone with a decent programming background (in addition to strong logic design), it was pretty obvious that one could design an address channel interface and embed two of these in an AXI interface. The other interfaces could be managed with, say, inheritance or embedding (i.e. “ISA” or “HASA”) to account for the differences. Alas it was not meant to be. Interface don’t support sub-interfaces nor inheritance which restricts their use to very simple cases. This is such a shame. I am not even going to wish that it be fixed in the next version of the standard. By the time these get addressed in 1800 and are implemented by the EDA vendors, I am hoping that I’ll have moved to strictly C based logic design.

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